It is known that the class B or class AB output stage using complementary push-pull transistors can be used to drive a load. FIG. 1 schematically illustrates such an output stage where a preamplifier, generally designated 2, generates drive signals to control first and second transistors 4 and 8 in a complementary manner such that the first transistor 4 is driven to be conducting during positive half cycles so as to pull the voltage at an output node 6 up towards the positive supply, +V, whereas a second transistor 8 is driven conducting during the negative half cycles so as to pull the voltage back to node 6 down towards the negative supply rail V−. In battery powered equipment the potential difference between the positive supply rail, +V, and the negative supply rail, which in practice is a local ground, can be quite small. Thus, in the context of hearing aids, headsets, music players or mobile telephones the voltage range might be as little as 1.5 volts. This restricts the voltage swing that can be obtained at the output node 6.
Where space is not an issue, then the peak to peak voltage range at the output transducer can be shifted by the inclusion of a DC blocking capacitor at the output node 6. However in order to achieve acceptable lower frequency bandwidth (for example 20 Hz), with audio applications typically having 16 Ohm loads, then the capacitor needs to have a size of 330 micro Farads. Within the context of integrated circuits, this represents a large component with an unacceptably high implementation cost.
In certain applications, it is possible to gain access to the terminals at either side of the output transducer and in such circumstances the effective voltage swing across the transducer can be increased by driving it within a “H bridge” circuit arrangement. However this is not always possible.
A common example of a device where reasonable to loud audio amplitude output is required, but where it is not possible to drive the transducer within an H bridge is the mobile telephone. Here, as illustrated in FIG. 2, the left and right earpiece transducers 10 and 12 share a common return line to a headphone jack, generally designated 14. Thus within this arrangement the common return must be held at a common voltage in order to reduce cross talk or to comply with the commonly used configuration of the headphone jack, and this is generally the local ground (i.e. negative battery potential) within the mobile device. This therefore reduces the output swing which can be provided to the left and right channels (designated A and B) from a stereo output amplifier 16. The common return line may also be shared with input devices, such as a microphone, which precludes use of an H bridge drive arrangement.
Returning to FIG. 1, one way to enhance the output amplitude would be to use a charge pump to generate a negative reference voltage, V−, such that the transistor 8 could pull the load voltage down from ground to V−. Charge pumps are well known to the person skilled in the art and consequently this is, at least initially, a very tempting possibility. However, within the context of an integrated circuit there are significant cost penalties incurred in building an integrated circuit where the output transistor 8 can connect to a negative reference voltage which lies below the ground voltage (e.g. as provided by the negative terminal of the battery) connected to the substrate of the integrated circuit and these problems will be discussed shortly. Whilst running the entire integrated circuit between the V+ and V− voltages would overcome the difficulties associated with integrated circuit fabrication, this would be at the cost of increasing the voltage difference across the integrated circuit as a whole, and hence increasing the power dissipation within the integrated circuit and consequently shortening battery life within a mobile device having such a circuit. This, therefore, is clearly undesirable, especially in devices where manufacturers strive to archive long “stand by” times.
It is worthwhile considering the formation of an integrated circuit in order to see where these problems arise. It is also worth bearing in mind that devices such as mobile telephones and Bluetooth headsets require the integration of highly complex digital processing circuitry together with RF and analog circuitry. It is also worth noting that the standard CMOS application process for creating digital circuitry can be used to form analog amplifiers. FIG. 3 schematically shows the formation of a P type transistor and an N type transistor within the standard CMOS fabrication process which is well known to the person skilled in the art and which is readily available at a large number of semiconductor fabrication facilities around the world. Within the standard CMOS chip a substrate 40 is doped with a P type impurity. Then, in order to form an N type transistor first and second regions 42 and 44 are doped with an N type impurity in order to form the source and drain of a field effect transistor. A conducting electrode 46 is then formed within the space between the regions 42 and 44 in order to form the gate. The gate 46 is insulated from the P type substrate 40 via a thin insulating layer 48 often of silicon dioxide. The interface between the N doped regions 42 and 44 and the P doped substrate 40 forms a parasitic diode, but this remains reversed biased, and consequently non-conducting, whilst the voltages within the N doped regions 42 and 44 remain higher than the voltage at the P type substrate 40.
In order to form a PMOS transistor it is necessary to dope a region of the substrate with an N type dopant in order to form an N-well 60. Then first and second regions 62 and 64 are doped with a P type material in order to form the source and drain of the PMOS field effect transistor. A gate electrode 66 is formed between the drain and source regions. The interface between the source and drain regions 62 and 64, and the N well 60 has the potential to form parasitic diodes, but these remain turned off provided that the potential in the N well is not less than the potential of the source and drain regions. In order to achieve this a further connection, known as a back gate 70 is provided such that the voltage at the N well can be held positive with respect to the potential of the P type substrate and the potentials of the source and drain terminals, or equal to the most positive of all three.
It can be seen from inspection of FIG. 1 in combination with FIG. 3 that where one of the first transistors is an NMOS device, trying to run the output node 6 at a voltage below the voltage of the P type substrate 40 will switch on parasitic diodes associated with the NMOS transistor.
However, if it is desired to be able to use the PMOS and NMOS transistors within a CMOS output stage capable of operating at a voltage below the potential of the P type substrate, then additional processing steps must be undertaken around the NMOS transistor in order to modify it. FIG. 4 shows a CMOS output stage where the NMOS transistor can operate at voltages below the potential of the substrate of the integrated circuit. In order to achieve this the standard NMOS transistor needs to be formed within its separate P well 80 which itself must be formed within an N well 82 within the P type substrate 40. Individual electrodes are connected to the P well 80 and the N well 82 such that the potential of these wells can be controlled in order to form back to back reverse biased diodes in order to prevent charge leakage from the source or drain terminals 42 and 44 of the NMOS transistor to the P type substrate. This formation of additional sub wells increases the complexity of fabrication of the semiconductor die.